- 3D and 2.5D analysis
- Full chip capacity
- Lab proven accuracy
- Power integrity sign-off
- Dynamic and static modes
- Thermal analysis in package
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Demo videos:
Videos Explaining Our Analog Analysis Flow:
- Data import
- Analysis
- Exploring results
Videos Explaining Our Digital Analysis Flow:
InVar 2.1 introduces Mixed Digital/Analog Sign-off
Layout/Temperature aware electrical simulation
InVar delivers:
- True-to-life electro-thermal analysis and simulation
- Analysis of analog and digital blocks in SoC environment
- Use of package and die parameters for highest accuracy
In the process of analog sign-off analysis, InVar calculates the sustained temperature and power over a defined period of time. Flexibility in defining starting temperatures, input stimuli, and simulation time allows user to calculate average and dynamic peak temperatures as well. The tool can run on multiple threads on multiple CPUs.
Analysis challenge
Accurate sign-off results cannot be achieved without concurrent analysis of parameters affecting IC behavior. Comprehensive Sign-off should consider power, signal timing, temperature, and die/packaging parameters of integrated circuits. Lack of correlation between simulated and real life behaviour of integrated circuits causes severe tape-out problems.
Increasing number of tools involved in sign-off analysis still provides fragmented picture that is far from real (measured) numbers.
InVar is the only tool on the market that implements concurrent analysis of parameters affecting the accuracy of sign-off data. InVar results correlate with measured parameters of physical samples.
Our solution
Invarian solves the problem of miscorrelation with unique approach to analysis process. Different InVar/SPICE analysis engines work in concert and take interdependence of power, signal timing, voltage, temperature, and package/die characteristics into account.
Contrary to other tools, all types of analysis are performed in continuous temperature/voltage space across the die (annotated with package parameters).
InVar does not use predefined corners for analysis. Sign-off analysis process is performed in the simulation environment that represents real life conditions
In the flow
InVar uses digital designs, analog designs, and "black box" models for SoC level analysis of power, temperature, timing, and effective voltage.
With use of "black box" models InVar could be first involved in the floorplan stage to get realistic thermal picture of the packaged design.
Analysis of digital design could be started as soon as placement in this design is done. For not routed nets, proprietary "virtual routing" model will be used to estimate parasitics.
Analog designs should have GDSII and SPICE netlist. Existing analog IP could be analyzed as soon as power budget for SoC modules is done and floorplan created.
InVar can generate trustable thermal and electrical (IBIS) IC models in pre-tapeout analysis run.
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