Analog solution

With introduction of analog design analysis functionality in InVar 2.0, the tool can perform accurate temperature/layout aware analog sign-off analysis with external electric circuit simulation engine. There are following benefits of joint solution:

  1. Analysis becomes very accurate with actual temperature assigned to each component.
  2. Accurate identification of electromigration issues
  3. Mapping of SPICE netlist to layout provides accurate locations for hotspots
  4. InVar solves full 3D heat transfer equation to assign temperature to design components. Input data to solve heat transfer problem includes block layout, temperature-dependent power of components, and power dissipated by other blocks in SoC design
  5. It is very easy to simulate analog module(s) in SoC environment; only minimal input is required for other blocks 

InVar 2.0 flow

To perform analog sign-off analysis InVar 2.0 requires:

  1. GDSII layout of analog module(s)
  2. Source or extracted SPICE netlist(s)
  3. SoC floorplan with placed blocks. User can estimate behavior of existing analog IP at floorplanning or tapeout stage
  4. Power and metallization numbers for other blocks. Blocks could be divided into sub-blocks for accurate simulation of hotspots
  5. Technology specific parameters like thermal conductivity, thickness, and package characteristics
  6. Environment conditions

In the process of data import, InVar performs state of the art mapping between the netlist and layout. This step is critical for accurate calculation of temperatures. Once mapping is done, the tool starts electro-thermal analysis with external circuit simulation engine.

In the process of co-analysis, InVar calculates the sustained temperature and power over a defined period of time. Flexibility in defining starting temperatures, input stimuli, and simulation time allows user to calculate average and dynamic peak temperatures as well. The tool can run on multiple threads on multiple CPUs. In case of multiple analog modules instantiated in SoC, the tool can utilize multiple electric circuit simulator and InVar licenses to avoid runtime degradation typical for sequential simulation runs.

Monte-Carlo approach to comprehensive electro-thermal sign-off is ineffective at analysis of systematic variation like temperature variation across the die. In this case, even if increasing the standard deviation, simulation will result in larger random variation but will very unlikely produce a temperature gradient. There are two issues:

  • overdesign for severe non-physical corners
  • underdesign for realizable scenarios.

Effects caused by packaging or die characteristics cannot be simulated using electrical circuit simulation alone. Temperature variation across the die is clearly systematic and requires a direct solution which Invarian offers. Rather than a random temperature variation or tightening of the parameters, it produces an accurate result with physically modeled temperature gradient.

Integrated analysis solution offered by Invarian helps designers to overcome existing analysis problems without additional flow complexity and runtime penalty.

 

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